Vera's Hardware Is Genuinely Impressive

NVIDIA's 45-page whitepaper describes Vera, its first server CPU with the custom Olympus core. The chip packs 88 cores on a monolithic die, each a 10-wide Arm v9.2 design. Highlights include value prediction, a graph prefetcher, 2 MB private L2 per core, 164 MB shared last-level cache, and eight LPDDR5X interfaces delivering 1.2 TB/s. Early independent testing by Phoronix shows Vera's geomean performance 10% above a 5 GHz EPYC 9575F, 1.55x a Xeon 6980P, and 1.63x Grace. That makes it the fastest Arm server CPU in public testing.

But the whitepaper's technical narrative is sloppy. NVIDIA tries to frame traditional SMT as time-slicing, presents a configurable NUMA topology as an unavoidable 32-node maze, and labels four SPEC components as "agentic benchmarks." The paper also uses undefined performance-counter ratios as causal proof and an unlabeled pictogram as a 1.8x reinforcement-learning result.

The SMT Strawman

Figure 5 contrasts "Traditional SMT (x86)" with NVIDIA's Spatial Multithreading. The x86 side shows branch predictor, decode, execution, load/store, and memory stages alternating between two threads. The caption claims Vera avoids "opportunistic time-sharing" by partitioning resources.

That's misleading. Real SMT implementations share stages differently. Fetch, decode, and allocate typically service threads per-cycle, while execution and memory stages are thread-agnostic and can handle micro-ops from both threads in the same cycle. Per-cycle selection can hide stalls in one thread by giving unused throughput to the other. Static partitioning, as NVIDIA implies, can leave resources idle if one thread is compute-bound.

NVIDIA's text emphasizes "determinism, isolation, and quality of service" — not performance. That's a valid design point for AI workloads, but the diagram suggests a performance advantage that isn't proven.

Also, the whitepaper reveals a 10,000-cycle penalty to switch back from dual-thread to single-thread mode on an Olympus core. That's a huge cost. Software must be very careful about launching a second thread. The paper gives no details on how out-of-order resources are partitioned, leaving SMT performance unknown.

The NUMA Misdirection

NVIDIA claims a two-socket x86 system can expose "as many as 32 NUMA domains," while Vera presents one per socket. That number is real — on many-chiplet EPYC systems, you can expose cache-local regions as separate NUMA nodes. But it's configurable. AMD's tuning guide lists NPS4, NPS2, NPS1, and NPS0 modes. The "LLC as NUMA" setting can expose each last-level-cache domain separately. So 32 nodes is an optional high-granularity configuration, not the default experience.

Vera's one domain per socket simplifies scheduling, but it doesn't eliminate physical distances. The die still has 88 cores, distributed cache, memory controllers, and a packet-switched fabric. A flat topology makes latencies more consistent, not nonexistent.

The paper's core-to-core heatmaps would quantify this, but they provide no core identities, no min/median/max table, no distribution, and no measurement procedure. "Up to 50% lower" captures the best result, not typical behavior.

Benchmark Shenanigans

NVIDIA selects four SPEC components and labels them "agentic benchmarks." That's a stretch. SPEC components measure specific workloads, not agentic AI tasks. The paper also uses undefined performance-counter ratios as causal proof — that's not rigorous.

The unlabeled pictogram that becomes a 1.8x reinforcement-learning result is the worst offender. Without a clear methodology, that number is meaningless.

What the Whitepaper Gets Right

Olympus's value prediction is notable. It's broader than AMD's Family 17h implementation, closer to Apple's. If the core predicts a result correctly, dependent instructions keep moving. That's a real advantage for latency-bound workloads.

The graph prefetcher isn't unique. Intel's Data-Dependent Prefetcher has been in silicon since 2022, and Granite Rapids has an Array of Pointers prefetcher that does the same producer-consumer idea. NVIDIA's implementation may handle more complex chains, but it's not new.

The neural branch predictor? AMD used a perceptron predictor in Piledriver (2012) and Zen 1. Zen 2 moved to TAGE for final prediction because it reduced mispredictions by 30%. So NVIDIA's "neural" predictor is an evolution, not a breakthrough.

The Real Story

Vera's hardware is strong enough that we can't dismiss the charts as fantasy. But the whitepaper's narrative is designed to make x86 look worse than it is. SMT and NUMA are complex topics, and NVIDIA oversimplifies them to make Vera look better.

As a developer, you should read the whitepaper with skepticism. Focus on the hardware specs and independent benchmarks, not the marketing spin. Wait for more testing once Vera ships in production systems. The Phoronix test was pre-production, one day, and NVIDIA chose the workloads and disallowed frequency/power monitoring.

What to Do Now

If you're evaluating Arm server CPUs, wait for Vera's general availability. Look for third-party benchmarks that run a broader set of workloads. For SMT, check how Vera's spatial multithreading performs in real multi-tenant scenarios. For NUMA, test both single-domain and multi-domain configurations to see which actually performs better for your workloads.

Don't trust the whitepaper's charts. Trust independent data.